This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-107632, filed Apr. 15, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor output circuit that can protect such a circuit as reverses the potentials of a collector and an emitter of a bipolar transistor.
A problem of an output circuit for driving an inductive load is that it is often damaged by a counter electromotive force from the inductive load.
FIG. 1 shows an example of a conventional output circuit. This output circuit 1 is comprised of a driving circuit 2, and a push-pull circuit consisting of a PNP transistor Q1 and an NPN transistor Q2. An output Vout of the output circuit 1 is connected to one of the terminals of an inductive load 3. As means for preventing an output section from being broken down by a counter electromotive force from the inductive load 3, a technique is known which connects protective diodes D1, D2 in parallel to the transistors Q1, Q2.
In the conventional output circuit, the diodes D1, D2 are added outside the semiconductor chip on which the output circuit is formed. Therefore, the total device size becomes very large. An object of the present invention is to integrate these protective diodes D1, D2 on the semiconductor chip to reduce the total device size.
Such a technique as shown in FIG. 1 allows the diodes D1, D2 to absorb currents IZH, IZL generated by a counter electromotive force from the inductive load 3 to preclude a voltage at the output terminal Vout of the power output circuit 1 from exceeding withstand voltages of the transistors Q1, Q2, thereby preventing breakdown of the transistors Q1, Q2.
The withstand voltages of the bipolar transistors Q1, Q2 constituting the push-pull circuit include collector-emitter withstand voltages Vceo1, Vceo2 for a forward operations of the Q1, Q2 and emitter-collector withstand voltages Veco1, Veco2 for reverse operations involving the reversal of voltages at the collector and emitter of the transistor.
As described above, when a counter electromotive force from the inductive load 3 increases the output terminal voltage Vout of the output circuit 1 beyond a power source voltage Vcc, the voltages at the collector and emitter of the PNP transistor Q1 are reversed. Then, when the potential difference exceeds Veco1, the transistor Q1 is broken down. In addition, if the output terminal voltage Vout of the output circuit 1 decreases below the ground, the voltages at the collector and emitter of the transistor Q2 are reversed. Then, if the potential difference exceeds Veco2, the transistor Q2 is broken down.
To sufficiently increase the values of the withstand voltages Veco1, Veco2 for reverse operations, impurities in base and emitter regions of the transistors Q1, Q2 must be diffused deeply for a low impurity concentration. This disadvantageously leads to an increased device size.
However, the recent demand for miniaturization of the device area has resulted in a tendency to reduce the withstand voltages Veco1, Veco2 for reverse operations, so that the protective diodes D1, D2 must have a diminished series resistance in order to improve their protective effects. To lessen the series resistance, larger devices must be used. Consequently, the size of the diodes D1, D2 becomes substantially equal to that of the transistors Q1, Q2, which constitute the output section, thereby hindering the size reduction of the output circuit 1.
Next, the structures of a vertical NPN transistor and a vertical PNP transistor will be described with reference to FIGS. 2A and 2B. FIG. 2A is a sectional view of a vertical NPN transistor fabricated using a miniaturized process. An N type epitaxial layer 13 is grown on a main surface of a P type semiconductor substrate 11 such as silicon, and a high-concentration buried N+ impurity diffused region (N+BL) 12 (hereafter referred to as a xe2x80x9cburied regionxe2x80x9d) is formed between the semiconductor substrate 11 and the N type epitaxial layer 13.
An NPN transistor is formed on the buried region 12. A device isolation region is formed in such a manner as to surround the NPN transistor. The device isolation region is comprised of a high-concentration P+ impurity diffused region (IsoP+) formed in the N type epitaxial layer 13, and a high-concentration P+ impurity diffused region (P+BL) connected to the P+ impurity diffused region 14 and extending to an interior of the semiconductor substrate 11. A P type base region 16 is formed in a device region on a surface of the N type epitaxial layer 13, the device region being surrounded by the device isolation region.
The P type base region 16 has a depth, for example, of 0.6 xcexcm from its surface. An N+ emitter region 17 is formed in the P type base region 16. The N+ emitter region 17 has a depth, for example, of 0.3 xcexcm from its surface. An N+ high-concentration collector region (DeepN+) 18 is formed in a surface region of the N type epitaxial layer 13 at a predetermined distance from the base region 16 so as to connect to the buried region 12. A base terminal (B) is formed in the P type base region 16, an emitter terminal (E) is formed in the N+ emitter region 17, and a collector terminal (c) is formed in the N+ high-concentration collector region 18, respectively, with an N+ contact region 19 being interposed between the N+ high-concentration collector region 18 and the collector terminal C.
FIG. 2B is a sectional view of a vertical PNP transistor formed using the miniaturized process. The same components as in FIG. 2A carry the same reference numerals and detailed description thereof is omitted. A P type collector region 20, an N type base region 21, and a P+ emitter region 22 are formed in the N type epitaxial layer 13, and a collector terminal (C), a base terminal (B), and an emitter terminal (E) are formed in the P type collector region 20, the N type base region 21, and the P+ emitter region 22, respectively.
Based on correspondence to the sectional structure of the vertical NPN transistor shown in FIG. 2A, a N type buried region is formed under the P type collector region 20, and at the same time a structure connecting to the N type buried region is formed which corresponds to 18, 19 in FIG. 2A. These components, however, are not directly relate to the present invention and have thus been omitted.
The value of an emitter-collector withstand voltage Veco of a bipolar transistor is determined by means of a reverse biased emitter junction, that is, when a leakage current arising from avalanche breakdown of a junction formed in a boundary between an emitter and a base regions of the bipolar transistor is conveyed to an interior of the base region, where it becomes an effective base current.
Accordingly, even in a base open state, an amplifying effect substantially equal to the flow of an effective base current occurs in the bipolar transistor, thereby reducing the value Veco below the breakdown voltage of the single reverse biased emitter junction (collector open emitter-base breakdown voltage Vebo), if the reverse current gain xcex2R of the bipolar transistor is larger than 1.
The meaning of the reverse current gain is as follows.
The ratio of the collector current to the base current through the bipolar transistor is a quantity generally called a current gain xcex2. However, in a circuit involving reversal of the potentials of a collector and emitter of a bipolar transistor (this is hereafter referred to as a reverse operation), the current gain xcex2 of the usual forward biased operation is changed to the current gain xcex2R of the reverse operation.
The current gain xcex2R in present specification is defined as the current gain for the reverse operation of the bipolar transistor.
The vertical NPN transistor shown in FIG. 2A and which is fabricated using the miniaturized process has a shallow emitter junction and an emitter region formed so as to have a high impurity concentration, whereby the emitter junction is subjected to a large amount of leakage current. In the base open state, the emitter-collector withstand voltage Veco has a low value of about 3V.
FIG. 3A shows a circuit for measuring Veco. This measuring circuit is configured to connect an ammeter between a collector of a base-open NPN transistor and the ground and to connect a power source 24 to an emitter of the transistor 23. Since the emitter of the NPN transistor is connected to a positive side of the power source 24, the voltage is principally applied to a reverse biased emitter junction.
An example of a measured current voltage characteristic is shown in FIG. 3B. This figure shows that the current rises rapidly with an applied voltage of 3V and that the emitter-collector breakdown voltage Veco has a low value of about 3V.
The value Veco of the vertical NPN transistor shown in FIG. 2A and which is fabricated using the miniaturized process has been described, but substantially similar results are obtained with the vertical PNP transistor shown in FIG. 2B and which is fabricated using the miniaturized process.
As described above, in a circuit including the reverse operation, the bipolar transistor is broken down at a very small value of Veco under a base-open or near-base-open condition. Therefore, measures for protecting such a circuit are required.
Although there have been circuits in which a bipolar transistor operates in a reverse direction under specific conditions, for example, as shown in FIG. 1, many recent circuits include a bipolar transistor that operates in the reverse direction under normal operation conditions.
For such a circuit, the reverse withstand voltage of the bipolar transistor, that is, the emitter-collector withstand voltage Veco is desirably increased to prevent breakdown. To sufficiently increase the withstand voltage, impurities must be deeply diffused in a base and an emitter of the transistor for a low concentration. This results in an increased device size to hinder chip size reduction.
The reversal of the potentials of a collector and an emitter of a bipolar transistor may occur, for example, in a car audio amplifier IC due to a counter electromotive force from an inductance component of a speaker wire acting as a load. In addition, in a large-signal operation of an power amplifier circuit such as shown in FIG. 13, the output potential may increase above that of an intermediate power source line or decrease below that of the intermediate power source line. In such a case, the potentials of a collector and an emitter of an output transistor are reversed.
In addition, in order to meet demands for protection against an abnormal condition of a semiconductor output circuit (for example, a user""s inappropriate operation), ground open output-ground shorting tests and Vcc open output-Vcc shorting tests on a breakdown mode specific to car ICs are being conducted.
A ground open output-ground shorting test for an amplifier IC comprising a push-pull type output circuit will be explained with reference to FIG. 4A.
According to the ground open output-ground shorting test, as shown in FIG. 4A, for an amplifier IC 28 which comprises an NPN transistor 26 and a PNP transistor 27 connected together in a push-pull manner, an output terminal of the amplifier IC 28 is shorted to a ground terminal of a power source 29 with a ground terminal of the amplifier IC removed from the ground terminal of the power source 29, as shown in FIG. 4A.
The moment the ground open output-ground shorting test is started, a large capacitor 30 is not charged which is located between the power source and the ground and which is externally connected to the amplifier IC 28. Accordingly, the emitter potential of the NPN transistor 26 is equal to the potential Vcc of the power source 29 while the collector potential of the NPN transistor 26 is equal to the ground potential of the power source 29, thereby reversing the potentials of the emitter and the collector.
At this point, if the emitter-collector withstand voltage Veco has a small value, the NPN transistor is broken down. Likewise, in the Vcc open output-Vcc shorting test shown in FIG. 4B, the potentials of the emitter and collector of the PNP transistor 27 are reversed, so that the PNP transistor 27 is broken down if the emitter-collector withstand voltage Veco has a small value. By shipping amplifier ICs that have passed these tests, users"" inappropriate operations can be dealt with.
As described above, the emitter-collector withstand voltage Veco has a smaller value than the emitter-base withstand voltage Vebo because a leakage current from a reverse biased emitter-base junction of a transistor is transported to an interior of a base thereof, where it becomes a base current and because avalanche breakdown, a source of the leakage current, is amplified by the transistor.
To sufficiently increase the value Veco, the emitter-base withstand voltage (withstand voltage of an emitter junction) must be raised by carrying out deep base-emitter diffusion of low impurity concentration or lessening the amplifying effect of a reverse operation of the transistor.
As described above, however, due to the ever decreasing size of devices, the recent tendency is to carry out shallow base-emitter diffusion of high impurity concentration, thereby gradually diminishing the emitter-collector withstand voltage Veco of bipolar transistors. Thus, it has gradually become difficult to protect semiconductor output circuits including such a reverse operation as reverses the potentials of a collector and an emitter of a bipolar transistor fabricated using the miniaturized process.
As described above, the conventional semiconductor output circuits has the problem that it is difficult to protect bipolar transistors including such a reverse operation as reverses the potentials of a collector and an emitter thereof.
The present invention is adapted to solve this problem, and it is an object thereof to provide a semiconductor output circuit that can increase the emitter-collector withstand voltage without the needs for deep base-emitter diffusion of low impurity concentration.
That is, a first additional circuit comprising a diode according to the present invention is characterized in that it is constructed by connecting a protective diode between a base and an emitter of a bipolar transistor constituting a semiconductor output circuit and in that a cathode of the protective diode is connected to a P type side of a base-emitter PN junction, while an anode of the protective diode is connected to an N type side of the base-emitter PN junction.
The anode and cathode of the diode are defined as electrodes wherein a high forward current flows through the diode when the potential of the anode is increased above that of the cathode.
Thus, if the first additional circuit comprising the protective diode is provided between the base and emitter of the bipolar transistor and a current gain xcex2R of the reverse operation of the bipolar transistor (collector current/base current) is larger than 1, then during the reverse operation of this bipolar transistor, a base current flowing through the first additional circuit operates the bipolar transistor on an ON side. Thus, the voltage between the emitter and collector of the bipolar transistor decreases.
In addition, a second additional circuit comprising a diode according to the present invention is characterized in that it is constructed by connecting a protective diode between a base and a collector of a bipolar transistor constituting an output circuit and in that an anode of the protective diode is connected to a P type side of a base-collector PN junction while a cathode of the protective diode is connected to an N type side of the base-collector PN junction.
If the second additional circuit comprising the protective diode is provided between the base and collector of the bipolar transistor in the above manner, the value Veco during a reverse operation of the bipolar transistor can be increased without the needs for deep base-emitter diffusion of low impurity concentration. Consequently, in particular, a semiconductor output circuit including a reverse operation in a base-open or near-base-open state can be effectively prevented from being broken down.
Specifically, the present invention provides a semiconductor output circuit comprising a push-pull circuit formed of a first bipolar transistor and a second bipolar transistor, and a protective diode configured to protect a bipolar transistor of at least any one of the first and second bipolar transistors, wherein the protective diode protects the bipolar transistor from a reverse operation of reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, the bipolar transistor has a value of a reverse current gain xcex2R larger than 1, and a cathode of the protective diode is connected to a P type side of a base-emitter PN junction of the bipolar transistor while an anode of the protective diode is connected to an N type side of the base-emitter PN junction of the bipolar transistor.
In addition, the present invention provides a semiconductor output circuit comprising a first power source line, a second power source line having a lower voltage than the first power source line, a push-pull circuit formed between the first and second power source lines and comprising a PNP and an NPN transistors, and a first and second protective diodes configured to protect the PNP and NPN transistors respectively, wherein the first and second protective diodes protect the PNP and NPN transistors from a reverse operation of reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, and each of the PNP and NPN transistors has a value of a reverse current gain xcex2R larger than 1,
and wherein the emitter of the PNP transistor is connected to the first power source line, the emitter of the NPN transistor is connected to the second power source line, the collector of the PNP transistor and the collector of the NPN transistor are connected together to constitute an output node of the push-pull circuit, a base of the PNP transistor is connected to an anode of the first protective diode, a cathode of the first protective diode is connected to the first power source line, a base of the NPN transistor is connected to a cathode of the second protective diode, and an anode of the second protective diode is connected to the second power source line.
In addition, the present invention provides a semiconductor output circuit comprising a bipolar transistor, a load circuit of the bipolar transistor, a circuit comprised of an active element or an impedance element a terminal of the circuit being connected to a connecting portion of the bipolar transistor and the load circuit, and a protective diode configured to protect the bipolar transistor, wherein the circuit comprised of the active element or the impedance element causes the reverse operation of the bipolar transistor reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, the protective diode protects the bipolar transistor from reverse operation, and an anode of the protective diode is connected to a P type side of a base-collector PN junction of the bipolar transistor while a cathode of the protective diode is connected to an N type side of the base-collector PN junction of the bipolar transistor.
In addition, the present invention provides a semiconductor output circuit comprising a first power source line, a second power source line having a lower voltage than the first power source line, an intermediate power source line having a voltage lower than that of the first power source line and higher than that of the second power source line, an output node of an NPN transistor to which a collector of the NPN transistor and one of the terminals of a load circuit are connected, a circuit comprised of an active element or an impedance element having one of its terminals connected to the output node, and a protective diode configured to protect the NPN transistor,
wherein the circuit comprised of the active element or the impedance element causes a reverse operation of the NPN transistor reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, and the protective diode protects the NPN transistor from the reverse operation,
and wherein an emitter of the NPN transistor is connected to the intermediate power source line, the other terminal of the load circuit is connected to the first power source line, the other terminal of the circuit comprised of the active element or the impedance element is connected to the second power source line, a cathode of the protective diode is connected to the collector of the NPN transistor, and an anode of the protective diode is connected to the base of the NPN transistor.
In addition, the present invention provides a semiconductor output circuit comprising a first power source line, a second power source line having a lower voltage than the first power source line, an intermediate power source line having a voltage lower than that of the first power source line and higher than that of the second power source line, an output node of an PNP transistor to which a collector of the PNP transistor and one of the terminals of a load circuit are connected, a circuit comprised of an active element or an impedance element having one of its terminals connected to the output node, and a protective diode configured to protect the PNP transistor,
wherein the circuit comprised of the active element or the impedance element causes a reverse operation of the PNP transistor reversing a polarity of a difference in potential between a collector and an emitter thereof in comparison to a normal bias state, and the protective diode protects the PNP transistor from the reverse operation, and
wherein an emitter of the PNP transistor is connected to the intermediate power source line, the other terminal of the load circuit is connected to the second power source line, the other terminal of the circuit comprised of the active element or the impedance element is connected to the first power source line, a cathode of the protective diode is connected to a base of the PNP transistor, and an anode of the protective diode is connected to the collector of the PNP transistor.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.